Epidemic algorithms for replicated database maintenance
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Routing in the Internet (2nd ed.)
Routing in the Internet (2nd ed.)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
IEEE Design & Test
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Nano, quantum and molecular computing: implications to high level design and validation
Nano, quantum and molecular computing: implications to high level design and validation
Hierarchical graph: a new cost effective architecture for network on chip
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
Journal of Systems Architecture: the EUROMICRO Journal
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
Hi-index | 0.00 |
Recent advances in the silicon technology is enabling the VLSI chips to accommodate billions of transistors; leading toward incorporating hundreds of heterogeneous components on a single chip. However, it has been observed that the scalability of chips is posing grave problems for the current interconnect architecture which is unable to cope with the growing number of components on a chip. To remedy the inefficiency of buses, researchers have explored the area of computer networks besides exploring parallel computing to come up with viable solutions for billion transistor chips. The outcome is a novel and scalable communication paradigm for future System on Chips (SoCs) called as Network on Chips (NoC). However, as the chip scales, the probability of both permanent and temporary faults is also increasing, making Fault Tolerance (FT) a key concern in scaling chips. Alpha particle emissions, Gaussian noise on channels are some of the reasons which introduce transient faults in the data. Besides that, due to electromigration of conductors, corrosion or aging factors, on-chip modules or links may suffer permanent damage. This paper proposes a comprehensive solution to deal with both permanent and transient errors affecting the VLSI chips. On the one hand we present an efficient packet retransmission mechanism to deal with packet corruption or loss due to transient faults. On the other hand, we propose a deterministic routing mechanism which routes packets on alternate paths when a communication link or a router suffers permanent failure.