Hierarchical graph: a new cost effective architecture for network on chip

Authors:
Alireza Vahdatpour;Ahmadreza Tavakoli;Mohammad Hossein Falaki
Affiliations:
Computer Engineering Department, Sharif University of Technology;Electrical Engineering Department, Sharif University of Technology;Computer Engineering Department, Sharif University of Technology
Venue:
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Year:
2005

Citing 3
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Abstract

We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads.