A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
Simulation of a signal arbitration algorithm for a sensor array
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
The LRD traffic impact on the NoC-based SoCs
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
System design of full HD MVC decoding on mesh-based multicore NoCs
Microprocessors & Microsystems
Hierarchical graph: a new cost effective architecture for network on chip
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Networks are becoming increasingly popular for use as on-chip interconnects. The problems with specification and performance evaluation increase with these solutions comparedto the traditional interconnect. This paper describes the design and simulation environment developed in the SoCBUS network-on-chip project. This environment is used as a basis to develop the benchmarking procedures necessaryto assess the performance of the networks. Two benchmarkingexamples are presented and used for evaluation of the SoCBUS network. These examples show how the simulationenvironment can be used to find the load bottleneck. They also show the appropriateness of the SoCBUS solution for (hard) real-time systems.