A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
X-means: Extending K-means with Efficient Estimation of the Number of Clusters
ICML '00 Proceedings of the Seventeenth International Conference on Machine Learning
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network on Chip Simulations for Benchmarking
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
How to use SimPoint to pick simulation points
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
A co-phase matrix to guide simultaneous multithreading simulation
ISPASS '04 Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software
A Generic Multi-Phase On-Chip Traffic Generation Environment
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Discovering and Exploiting Program Phases
IEEE Micro
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
A flexible framework for communication evaluation in SoC design
International Journal of Parallel Programming
Statistical physics approaches for network-on-chip traffic characterization
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The LRD traffic impact on the NoC-based SoCs
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Comprehensive on-chip traffic generator model for SoC design and synthesis
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Netrace: dependency-driven trace-based network-on-chip simulation
Proceedings of the Third International Workshop on Network on Chip Architectures
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Network-on-chip traffic modeling for data flow applications
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
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During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently done using traffic generators which emulate the SoC components (IPs) behavior: processors, hardware accelerators, etc. Traffic generated by processor-like IPs is highly non-regular, it must be decomposed into program phases. We propose an original feature for NoC prototyping, inspired by techniques used in processor architecture performance evaluation: the automatic detection of traffic phases. Integrated in our NoC prototyping environment, this feature permits to have a completely automatic toolchain for the generation of stochastic traffic generators. We show that our traffic generators emulate precisely the behavior of processors and that our environment is a versatile tool for networks-on-chip prototyping. Simulations are performed in a SystemC-based simulation environment with a mesh network-on-chip (DSPIN) and a processor running MP3 decoding applications.