On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Wide area traffic: the failure of Poisson modeling
IEEE/ACM Transactions on Networking (TON)
An introduction to econophysics: correlations and complexity in finance
An introduction to econophysics: correlations and complexity in finance
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Self-Similar Network Traffic and Performance Evaluation
Self-Similar Network Traffic and Performance Evaluation
Networks on chip
Buffer space optimisation with communication synthesis and traffic shaping for NoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Theory and Applications of Fractional Differential Equations, Volume 204 (North-Holland Mathematics Studies)
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Quantum-like effects in network-on-chip buffers behavior
Proceedings of the 44th annual Design Automation Conference
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
ICCPS '12 Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
On bottleneck analysis in stochastic stream processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
A cyber-physical system approach to artificial pancreas design
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Proceedings of the International Conference on Computer-Aided Design
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In order to face the growing complexity of embedded applications, we aim to build highly efficient Network-on-Chip (NoC) architectures which can connect in a scalable manner various computational modules of the platform. For such networked platforms, it is increasingly important to accurately model the traffic characteristics as this is intimately related to our ability to determine the optimal buffer size at various routers in the network and thus provide analytical metrics for various power-performance trade-offs. In this paper, we show that the main limitations of queueing theory and Markov chain approaches to solving the buffer sizing problem can be overcome by adopting a statistical physics approach to probability density characterization which incorporates the power law distribution, correlations, and scaling properties exhibited within an NoC architecture due to various network transactions. As experimental results show, this new approach represents a breakthrough in accurate traffic modeling under non-equilibrium conditions. As such, our results can be directly used to solve the buffer sizing problem for multiprocessor systems where communication happens via the NoC approach.