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Event Model Interfaces for Heterogeneous System Analysis
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A Network on Chip Architecture and Design Methodology
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DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Application-specific workload shaping in multimedia-enabled personal mobile devices
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Application-specific workload shaping in multimedia-enabled personal mobile devices
ACM Transactions on Embedded Computing Systems (TECS)
Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A path-load based adaptive routing algorithm for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Statistical physics approaches for network-on-chip traffic characterization
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Journal of Signal Processing Systems
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Task migration for fault-tolerance in mixed-criticality embedded systems
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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This paper addresses communication optimisation for applications implemented on networks-on-chip. The mapping of data packets to network links and the timing of the release of the packets are critical for avoiding destination contention. This reduces the demand for communication buffers with obvious advantages in chip area and energy savings. We propose a buffer need analysis approach and a strategy for communication synthesis and packet release timing with minimum communication buffer demand that guarantees worst-case response times.