High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Circular Buffered Switch Design with Wormhole Routing and Virtual Channels
ICCD '98 Proceedings of the International Conference on Computer Design
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Buffer space optimisation with communication synthesis and traffic shaping for NoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Virtual Channels Planning for Networks-on-Chip
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
IEEE Transactions on Computers
On-Chip Networks
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as a scalable communication fabric for interconnecting the cores. With increasing core counts, there is a corresponding increase in communication demands in multi-core designs to facilitate high core utilization, and a consequent critical need for high-performance NoCs. Another megatrend in advanced technologies is that power has become the most critical design constraint. In this paper, we focus on trace-driven virtual channel (VC) allocation in application-specific NoCs. We propose a new significant VC failure metric to capture the impact of VCs on network performance and efficiently drive NoC optimization. Our proposed metaheuristics achieve up to 38% reduction in the number of VCs under a given average packet latency constraint. In addition, compared to a recently proposed trace-driven VC allocation approach [13], we obtain up to an O(|L|) speedup, where |L| is total number of links in the network, with no degradation in the quality of results.