Multiprocessor networks with small buffers: theory and simulation
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Latency and saturation in networks with finite buffers
Proceedings of the 14th Communications and Networking Symposium
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
An analytical model for on-chip interconnects in multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Recent research in On-chip interconnection networks (OCINs) research has shown that the design of buffers in the router significantly influences the power, area overhead and overall performance of the network. In this paper, we propose a low-power, low-area OCIN architecture by reducing the number of buffers within the router. To minimize the performance degradation due to the reduced buffer size, we use the existing repeaters along the inter-router channels to double as buffers when required. At low network loads, the proposed adaptive channel buffers function as conventional repeaters propagating the signals. At high network loads, the adaptive channel buffers function as storage elements in addition to the router buffers. We evaluate the proposed adaptive channel buffers with both static and dynamic buffer allocation policies in the 90nm technology node, using 8脳8 mesh and folded torus network topologies. Simulation results using the SPLASH-2 suite and synthetic traffic show that by reducing the router buffer size our proposed architecture achieves nearly 40% savings in router buffer power, 30% savings in overall network power and 40% savings in area, with only a marginal 1-5% drop in throughput under dynamic buffer allocation and about 10-20% drop in throughput for statically assigned buffers.