The turn model for adaptive routing
Journal of the ACM (JACM)
Impact of selection functions on routing algorithm performance in multicomputer networks
ICS '97 Proceedings of the 11th international conference on Supercomputing
Proceedings of the 6th international workshop on Hardware/software codesign
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Performance tuning of adaptive wormhole routing through selection function choice
Journal of Parallel and Distributed Computing
On the Influence of the Selection Function on the Performance of Networks of Workstations
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Centralized end-to-end flow control in a best-effort network-on-chip
Proceedings of the 5th ACM international conference on Embedded software
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
IEEE Transactions on Computers
Secure Memory Accesses on Networks-on-Chip
IEEE Transactions on Computers
On the Potentials of Segment-Based Routing for NoCs
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
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The fact that latency increases abruptly once the on-chip network is saturated indicates that it is necessary to devise an effective flow control strategy. Through tracing the status of the network buffer space we found that the payload of the on-chip network cannot get beyond an upper bound to avoid vicious congestion. Specifically, quarter of the total network buffer space is such a threshold, which is termed Quarter Load Threshold (QLT). Based on this fact we present the Quarter Load Threshold (QLT) flow control strategy. The performance of the proposed strategy is evaluated by the open source simulator Noxim [Noxim: Network-on-Chip Simulator, http://sourceforge.net/projects/noxim, 2008]. Simulation results show that the on-chip network runs smoothly and no serious congestion is encountered any more.