Control systems engineering
Computer Networks
Modern Control Systems
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Centralized end-to-end flow control in a best-effort network-on-chip
Proceedings of the 5th ACM international conference on Embedded software
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Survey Constrained model predictive control: Stability and optimality
Automatica (Journal of IFAC)
A taxonomy for congestion control algorithms in packet switching networks
IEEE Network: The Magazine of Global Internetworking
A monitoring-aware network-on-chip design flow
Journal of Systems Architecture: the EUROMICRO Journal
Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures
ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
ROAdNoC: runtime observability for an adaptive network on chip architecture
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
Journal of Parallel and Distributed Computing
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
MPSoCs run-time monitoring through networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the Third International Workshop on Network on Chip Architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An abacus turn model for time/space-efficient reconfigurable routing
Proceedings of the 38th annual international symposium on Computer architecture
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Proceedings of the 4th International Workshop on Network on Chip Architectures
Status data and communication aspects in dynamically clustered network-on-chip monitoring
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
Cost-effective contention avoidance in a CMP with shared memory controllers
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
RISO: relaxed network-on-chip isolation for cloud processors
Proceedings of the 50th Annual Design Automation Conference
Smart hill climbing for agile dynamic mapping in many-core systems
Proceedings of the 50th Annual Design Automation Conference
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we introduce a new communication service, congestion-controlled best-effort (CCBE). The load offered to a CCBE connection is controlled based on congestion measurements in the NoC. Link utilization is monitored as a congestion measure, and transported to a Model Predictive Controller (MPC). Guaranteed bandwidth and latency connections in the NoC are used for this, to assure progress of link utilization data in a congested NoC. We also present a simple but effective model for link utilization for the model-based predictions. Experimental results show that the presented strategy is effective and has reaction speeds of several microseconds which is considered acceptable for realtime embedded systems.