A stop-and-go queueing framework for congestion management
SIGCOMM '90 Proceedings of the ACM symposium on Communications architectures & protocols
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction
IEEE Computer Architecture Letters
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Credit-based flow control for ATM networks
IEEE Network: The Magazine of Global Internetworking
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
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This paper presents a self-reconfigurable channel data buffering scheme and circuit design for next-generation network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. During network congestion, the buffering scheme realizes adaptive flow control by reconfiguring the channel buffers for online data storage. Once congestion is alleviated, data transmission resumes from the foremost buffer stage, thereby improving NoC throughput. It also achieves system-level power optimization through an integrated hardware-software codesign approach. Using software techniques such as dynamic voltage and frequency scaling, optimal voltages and frequencies are provided to the system through a hardware-based single-inductor multiple-output dc-dc converter platform. Meanwhile, power dissipation is further minimized through switched-capacitor delay control modules. A CMOS IC prototype has been fabricated, with 16-bit data transmission capability. It demonstrates 58.9% power saving over conventional designs. To achieve the same throughput, it consumes only 45.4 % power of the best prior art. The flexibility of the butTering scheme, along with the integrated power management solution, allows it to be applied to most existing commercial NoC architectures.