Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Dynamic power saving in fat-tree interconnection networks using on/off links
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Dynamic evolution of congestion trees: analysis and impact on switch architecture
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
On the correct sizing on meshes through an effective congestion management strategy
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Power-aware fat-tree networks using on/off links
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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We compare techniques that dynamically scale the voltage of individual network links to reduce power consumption with an approach in which all links in the network are set to the same voltage and adaptive routing is used to distribute load across the network. Our results show that adaptive routing with static network link voltages outperforms dimension-order routing with dynamic link voltages in all cases, because the adaptive routing scheme can respond more quickly to changes in network demand. Adaptive routing with static link voltages also outperforms adaptive routing with dynamic link voltages in many cases, although dynamic link voltage scaling gives better behavior as the demand on the network grows.