The Markov-modulated Poisson process (MMPP) cookbook
Performance Evaluation
Connection-wise end-to-end performance analysis of queuing networks with MMPP inputs
Performance Evaluation
An Analytical Model of Adaptive Wormhole Routing in Hypercubes in the Presence of Hot Spot Traffic
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
IEEE Transactions on Computers
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Performance Evaluation - Special issue: Distributed systems performance
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Design space exploration and prototyping for on-chip multimedia applications
Proceedings of the 43rd annual Design Automation Conference
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A performance model for analysis of heterogeneous multi-cluster systems
Parallel Computing
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis
IEEE Transactions on Computers
Analytical Modelling of Pipelined Circuit Switching with Bursty and Hot-Spot Traffic
HPCC '08 Proceedings of the 2008 10th IEEE International Conference on High Performance Computing and Communications
Non-uniform fat-meshes for chip multiprocessors
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
IEEE Transactions on Parallel and Distributed Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Embedded Computing Systems (TECS)
ICETET '09 Proceedings of the 2009 Second International Conference on Emerging Trends in Engineering & Technology
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Journal of Systems and Software
On the defense of the distributed denial of service attacks: an on-off feedback control approach
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
IEEE Journal on Selected Areas in Communications
Autonet: a high-speed, self-configuring local area network using point-to-point links
IEEE Journal on Selected Areas in Communications
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The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects. Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection network under bursty multimedia traffic and nonuniform message destinations. Extensive simulation experiments are conducted to validate the accuracy of the model, which is then adopted as a cost-efficient tool to investigate the effects of bursty multimedia traffic with nonuniform destinations on the network performance.