A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
Proceedings of the 45th annual Design Automation Conference
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Performance modeling of n-dimensional mesh networks
Performance Evaluation
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Delay analysis of wormhole based heterogeneous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
Optimizing heterogeneous NoC design
Proceedings of the International Workshop on System Level Interconnect Prediction
Flexible router architecture for network-on-chip
Computers & Mathematics with Applications
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
User satisfaction aware routing decisions in NOC
Proceedings of the Sixth International Workshop on Network on Chip Architectures
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The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of area and significant leakage power, especially at nanoscale. To remedy this situation, we propose a novel approach for customizing the virtual channels allocation based on the traffic characteristics of the target application. Towards this end, we first develop an algorithm that calculates the port contention rates and expected bandwidth at each router in the network. Using this information, we add VCs only to the channels with the highest bandwidth usage. Our simulation results involving synthetic and real applications show more than 40% buffer savings compared to uniform VC allocation, while achieving similar performance levels.