Performance of the Direct Binary n-Cube Network for Multiprocessors
IEEE Transactions on Computers
Steady-state simulation of queueing processes: survey of problems and solutions
ACM Computing Surveys (CSUR)
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
Performance evaluation of deterministic wormhole routing in k-ary n-cubes
Parallel Computing
Analysis of fully adaptive wormhole routing in tori
Parallel Computing
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
IEEE Transactions on Computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Delay Model for Router Microarchitectures
IEEE Micro
Hypercube Communication Delay with Wormhole Routing
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing
IEEE Transactions on Parallel and Distributed Systems
High-speed local area networks using wormhole routing: modeling and extensions
High-speed local area networks using wormhole routing: modeling and extensions
A Performance Model for Wormhole-Switched Interconnection Networks under Self-Similar Traffic
IEEE Transactions on Computers
Performance Modeling of Fully Adaptive Wormhole Routing in 2-D Mesh-Connected Multiprocessors
MASCOTS '04 Proceedings of the The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
AMS '07 Proceedings of the First Asia International Conference on Modelling & Simulation
Virtual Channels Planning for Networks-on-Chip
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the first analytical performance model of the n-D mesh using adaptive wormhole routing. To this end, we calculate the exact traffic rates over different network channels and determine the average message latency by averaging over the message latency values corresponding to all possible source-destination pairs of nodes in the network. Simulation results show that the proposed model can predict the message latency fairly accurately under various working conditions.