High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Circular Buffered Switch Design with Wormhole Routing and Virtual Channels
ICCD '98 Proceedings of the International Conference on Computer Design
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Cache Array Architecture Optimization at Deep Submicron Technologies
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Router with centralized buffer for network-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Low power nanoscale buffer management for network on chip routers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
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Network-on-Chip (NoC)architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the ptimization of NoC architectures has shown that the design of buffers in the NoC routers influences the power consumption, area overhead and performance of the entire network. In this paper, we propose a low-power area-efficient NoC architecture by reducing the number of router buffers. As a reduction in the number of buffers degrades the network's performance, we propose to use the existing repeaters along the inter-router links as adaptive channel buffers for storing data when required. We evaluate the proposed adaptive communication channel buffers under static and dynamic buffer allocation in 8 x 8 mesh and folded torus network topologies. Simulation results show that reducing the router buffer size in half and using the adaptive channel buffers reduces the buffer power by 40-52% and leads to a 17-20% savings in overall network power with a 50% reduction in router area. The design with dynamic buffer allocation shows a marginal 1-5% drop in performance, while static buffer allocation shows a 10-20% drop in performance, for various traffic patterns.