Router with centralized buffer for network-on-chip

Authors:
Ling Wang;Jianwen Zhang;Xiaoqing Yang;Dongxin Wen
Affiliations:
Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China;Harbin Institute of Technology, Harbin, China
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

Network-on-Chip (NoC) architectures are proposed as a possible solution to the wiring challenge. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a centralized buffer structure, which dynamically allocates buffer resources according to network traffic conditions. This centralized buffer management scheme increases the buffer utilization and decreases the overall buffer use on an average of 50% in our case study analysis compared to a fixed buffer assignment strategy. The area overhead can be traded-off against the flexibility of on-demand buffer management.