ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

Authors:
Chrysostomos A. Nicopoulos;Dongkook Park;Jongman Kim;N. Vijaykrishnan;Mazin S. Yousif;Chita R. Das
Affiliations:
University Park, PA 16802, USA;University Park, PA 16802, USA;University Park, PA 16802, USA;University Park, PA 16802, USA;Intel Corp., Hillsboro, OR;University Park, PA 16802, USA
Venue:
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Year:
2006

Citing 31
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Abstract

The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25% on average over an equal-size generic router buffer, or similar performance using a 50% smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30% and 34%, respectively, based on synthesized designs in 90 nm technology.