Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Performance of the Direct Binary n-Cube Network for Multiprocessors
IEEE Transactions on Computers
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
Flexible oblivious router architecture
IBM Journal of Research and Development
Evaluation of queue designs for true fully adaptive routers
Journal of Parallel and Distributed Computing
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A DAMQ shared buffer scheme for network-on-chip
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
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This paper describes a new approach to implement Dynamically Allocated Multi-Queue (DAMQ) switching elements using a technique called "self-compacting buffers". This technique is efficient in that the amount of hardware required to manage the buffers is relatively small; it offers high performance since it is an implementation of a DAMQ. The first part of this paper describes the self-compacting buffer architecture in detail, and compares it against a competing DAMQ switch design. The second part presents extensive simulation results comparing the performance of a self-compacting buffer switch against an ideal switch including several examples of k-ary n-cubes and delta networks. In addition, simulation results show how the performance of an entire network can be quickly and accurately approximated by simulating just a single switching element.