The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Spider: A High-Speed Network Interconnect
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
A High-Throughput Distributed Shared-Buffer NoC Router
IEEE Computer Architecture Letters
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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The input buffers of the current packet-switched Network-on-Chip (NoC) architectures consume a significant portion of the total power of the interconnection network. Reducing the size of input buffers would result in degraded performance, while eliminating all buffers would result in increased power at high network load. In this article, we propose DXbar: an innovative dual-crossbar design. By combining the advantages of buffered and bufferless networks, we achieve at least 20% performance improvement in terms of throughput and latency, and at least 20% power saving over buffered networks with virtual channels. Furthermore, DXbar can outperform current bufferless networks with deflecting and dropping protocols while consuming at most half of the power.