Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
On-line Fault Detection and Location for NoC Interconnects
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NoC Power Estimation at the RTL Abstraction Level
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Reliability aware NoC router architecture using input channel buffer sharing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Self-timed thermal sensing and monitoring of multicore systems
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Investigation of Transient Fault Effects in an Asynchronous NoC Router
PDP '10 Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach
COMPSAC '11 Proceedings of the 2011 IEEE 35th Annual Computer Software and Applications Conference
A Fault Tolerant Hierarchical Network on Chip Router Architecture
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.