NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Exploiting ECC Redundancy to Minimize Crosstalk Impact
IEEE Design & Test
Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
NoC Power Optimization Using a Reconfigurable Router
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
International Journal of High Performance Systems Architecture
Journal of Electronic Testing: Theory and Applications
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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As the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. However, faults can affect the routers services, thus compromising the communication integrity and the whole operation of the system. This work proposes the simultaneous use of Reconfiguration, Hamming Code and Triple Modular Redundancy (TMR) to ensure fault tolerance in the FIFOs and links of the network-on-chips (NoCs). The proposed router can dynamically stop using faulty buffers and, to sustain performance, borrow other buffer units from its neighbor channels whenever necessary. The Hamming Code protects the data in the links against a fault in a wire, while TMR is used to protect the control of the FIFO. The new router increases the reliability in 63% and shows low latency and power when compared to the original router. The HW overhead is 77% more gates, used to improve the yield and the system lifetime in comparison to the usage of the reconfigurable router just for performance increase in the NoC.