Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel processing for block ciphers on a fault tolerant networked processor array
International Journal of High Performance Systems Architecture
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
International Journal of Computer Applications in Technology
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We present an adaptive error control method for switch-to-switch links in a variable noise environment, to meet reliability requirements and achieve energy-efficiency. Unlike worst-case error correction coding (ECC), the proposed method is capable of selecting the most effective ECC scheme based on predicted link quality at runtime. Our method configures the ECC codec to obtain the desired error correction strength using a set of single-error correction (SEC) codes combined with interleaving. The method can effectively handle multi-cycle and adjacent multi-wire errors existing on switch-to-switch links. An experimental case study shows that the adaptive method can increase the energy-efficiency by up to 19% over a fixed ECC scheme, for a given residual flit error rate. Furthermore, energy reduction affected by different multi-wire and multi-cycle noise scenarios are compared.