Journal of Parallel and Distributed Computing
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Proceedings of the 2002 international symposium on Low power electronics and design
Deep-Submicron Microprocessor Design Issues
IEEE Micro
A 29.5 Tflops simulation of planetesimals in Uranus-Neptune region on GRAPE-6
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
An overview of the BlueGene/L Supercomputer
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Computational Aspects of VLSI
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Electronic System, Platform, and Package Codesign
IEEE Design & Test
Proceedings of the 43rd annual Design Automation Conference
A cell library for low power high performance CMOS voltage-mode quaternary logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Proceedings of the 4th international conference on Computing frontiers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Enhancing operating system support for multicore processors by using hardware performance monitoring
ACM SIGOPS Operating Systems Review
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Leakage-efficient design of value predictors through state and non-state preserving techniques
The Journal of Supercomputing
Reducing the associativity and size of step caches in CRCW operation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Token3D: reducing temperature in 3d die-stacked CMPs through cycle-level power control mechanisms
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
A UML 2.0 profile to model block cipher algorithms
ECMFA'10 Proceedings of the 6th European conference on Modelling Foundations and Applications
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches
International Journal of Embedded and Real-Time Communication Systems
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
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As power becomes increasingly important, the cubic trade-off between time and power (T3P = constant) forces designers to use relatively cheap area to increase performance rather than the expensive power required by higher clock rates. As designers focus on power, the question of optimal power-oriented architectures is apparent.