Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
SH3: High Code Density, Low Power
IEEE Micro
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The Design of Way-Prediction Scheme in Set-Associative Cache for Energy Efficient Embedded System
CMC '09 Proceedings of the 2009 WRI International Conference on Communications and Mobile Computing - Volume 03
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Fast Way-Prediction Instruction Cache for Energy Efficiency and High Performance
NAS '09 Proceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage
Low Power Branch Predictor for Embedded Processors
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
Computer Architecture, Fifth Edition: A Quantitative Approach
Computer Architecture, Fifth Edition: A Quantitative Approach
NESEA '11 Proceedings of the 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications
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This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU most recently used buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP energy delay product up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.