A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches
International Journal of Embedded and Real-Time Communication Systems
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Embedded System develops rapidly, functions turn into more complicate, and multi-media applications are growing daily and they consume more electrical power. Therefore, how to improve stand-by time will become a very important issue. Related researches indicate that the power consumption of processor cache is accounted for a big proportion. Way-prediction and LRU (Least Recently Used) algorithms improve hit rate and would help in reducing the number of tag comparisons, and therefore save energy consumption. In this paper, we use MRU (Most Recently Used) table to record the most used block for each index and use Modified Pseudo LRU (MPLRU) Replacement algorithm for reducing hardware complexity and cache miss rate.Experiments show our prediction hit rate reach 90.15%, thus save 64.12% energy. The experimental results are obtained by using Wattch cache simulator for SPEC95 benchmarks.