A cell library for low power high performance CMOS voltage-mode quaternary logic

Authors:
Ricardo C. G. da Silva;Henri Boudinov;Luigi Carro
Affiliations:
UFRGS - PGMICRO, Porto Alegre, RS, Brazil;Instituto de Física - UFRGS, Porto Alegre, RS, Brazil;Escola de Engenharia - UFRGS, Porto Alegre, RS, Brazil
Venue:
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Year:
2006

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Abstract

A new method to implement high performance and low power quaternary circuits using multi-threshold transistors and 3 power supply lines is presented in this work. Some specific basic gates like inverter, NMIN and NMAX circuits are presented together with a look-up table that can be used to perform any logic function. These basic circuits are used to implement arithmetic circuits. A quaternary full adder is demonstrated and compared to equivalent binary circuit showing higher speed, low consumption with a low area overhead. The circuits were simulated with the Spice tool using TSMC 0.18μm technology.