Circuits for multiple valued logic—a tutorial and appreciation
MVL '76 Proceedings of the sixth international symposium on Multiple-valued logic
An implementation of the stefanelli multi-valued parallel divider array
MVL '76 Proceedings of the sixth international symposium on Multiple-valued logic
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
TTL circuits for a 4-valued bus a way to reduce package and interconnections
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Some I2L circuits for multiple-valued logic
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Four-valued threshold logic full adder circuit implementations
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
A simultaneous, radix four, I2L multiplier mechanized via repeated addition
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Fault secure multiple-valued logic networks
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
A Minimization Technique for Multiple-Valued Logic Systems
IEEE Transactions on Computers
High Density Integrated Computing Circuitry with Multiple Valued Logic
IEEE Transactions on Computers
Design of Ternary COS/MOS Memory and Sequential Circuits
IEEE Transactions on Computers
Implementing Parallel Counters with Four-Valued Threshold Logic
IEEE Transactions on Computers
A High Data-Rate Digital Output Correlator Design
IEEE Transactions on Computers
Multivalued I2L Circuits for TSC Checkers
IEEE Transactions on Computers
Complex Number Arithmetic with Odd- Valued Logic
IEEE Transactions on Computers
Multiple-Valued Logic Charge-Coupled Devices
IEEE Transactions on Computers
Synthesis of Discrete Functions Using I2L Technology
IEEE Transactions on Computers
Logic Design of Multivalued I2L Logic Circuits
IEEE Transactions on Computers
On the Design of Three-Valued Asynchronous Modules
IEEE Transactions on Computers
A Many-Valued Algebra for Switching Systems
IEEE Transactions on Computers
A Design for Multiple-Valued Logic Gates Based on MESFET's
IEEE Transactions on Computers
Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks
IEEE Transactions on Computers
A Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks
IEEE Transactions on Computers
Implementation of Ternary Circuits with-Binary Integrated Circuits
IEEE Transactions on Computers
Multivalued Integrated Injection Logic
IEEE Transactions on Computers
Ternary Scan Design for VLSI Testability
IEEE Transactions on Computers
Compact Signed-Digit Adder Using Multiple-Valued Logic
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
On Designing of 4-Valued Memory with Double-Gate TFT
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
A cell library for low power high performance CMOS voltage-mode quaternary logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Introduction Multiple-Valued Logic
IEEE Transactions on Computers
IEEE Transactions on Computers
Constraints in the design of CMOS MVL circuits
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Binary to modified trinary number system conversion and vice-versa for optical super computing
Natural Computing: an international journal
A hybrid memory cell using Single-Electron transfer
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Modeling a single electron turnstile in HSPICE
Proceedings of the great lakes symposium on VLSI
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Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in integrated circuit technology. Multiple-valued logic has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Besides reduction in chip area, MVL offers other benefits such as the potential for circuit test. This paper describes the historical and technical background of MVL, and areas of present and future application. It is intended, as well, to serve as a tutorial for the nonspecialist.