Regular Ternary Logic Functions Ternary Logic Functions Suitable for Treating Ambiguity
IEEE Transactions on Computers
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
The Prospects for Multivalued Logic: A Technology and Applications View
IEEE Transactions on Computers
Carbon-nanotube-based voltage-mode multiple-valued logic design
IEEE Transactions on Nanotechnology
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
IEEE Transactions on Nanotechnology
A novel and improved design of a ternary CNTFET-based cell
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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In this paper, we propose new universal designs of ternary-valued logic (TVL) with high-speed, low-power and full swing output using carbon nanotube FETs (CNTFETs). All of the TVL functions (3^9 functions) can be implemented in these designs. Ternary value logic is a promising alternative to binary logic due to the reduced integrated circuit (IC) interconnects and chip area. Therefore, a universal design of TVL is a good direction for the future of FPGA design using CNTFET. In this paper, new universal designs of ternary-valued logic based on CNTFETs are proposed and compared with the existing resistive-load CNTFET universal TVL designs. Extensive simulations have been performed in HSPICE to investigate the distribution of power consumption and the delay of the CNTFET-based universal cells due to variations in the supply voltage, the diameter of the CNT, and the room temperature. Simulation results show that the proposed universal TVL designs result in significantly lower power consumption and delay compared with previous resistive-load CNTFET universal TVL implementations.