Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Challenges and Directions for Low-Voltage SRAM
IEEE Design & Test
Carbon-nanotube-based voltage-mode multiple-valued logic design
IEEE Transactions on Nanotechnology
Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection
IEEE Transactions on Nanotechnology
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
IEEE Transactions on Nanotechnology
| Hi-index | 0.00 |
A novel ternary CNTFET-based SRAM cell is proposed in this paper; the operation of this CNTFET SRAM is nearly independent of the ternary values, therefore it is said to be balanced. Different from previous ternary cells, the proposed cell does not require a read buffer for changing the voltage level of the read bit line, because it uses additional CNTFETs to sink the bit lines to ground. By using four additional CNTFETs for ternary operation, a conventional (two-valued) sense amplifier is then used for output response. The contribution of this paper is not restricted to the design of the SRAM cell, but also the systematic modifications of the CNTFETs to substantially improve specific performance metrics. CNTFET features (such as sizing) and performance metrics (such as SNM, power delay product (PDP) and write/read times) are considered and assessed in detail. Extensive simulation results are provided to show that the proposed ternary SRAM cell has better performance compared to a previous CNTFET-based ternary cell as well as binary-based cells (implemented by either MOSFET or CNTFET).