A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
The Prospects for Multivalued Logic: A Technology and Applications View
IEEE Transactions on Computers
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In this correspondence, a new scheme is proposed in which ternary clocking signals are used to replace binary clocking signals in VLSI scan-testing designs. This scheme has the same advantage of high testability as the binary scan method [1], but it eliminates the mode- selecting signal line. Since this mode-selecting line must be routed to each flip-flop in the binary scan scheme, the saving is significant in reducing the circuit interconnection complexity and chip area. This correspondence describes the new ternary scheme in detail, and also suggests appropriate circuit designs using CMOS technology. Furthermore, comparisons are made between ternary scan and binary scan [3] and between ternary scan and a scan scheme using binary with a local decoder [2].