A cell library for low power high performance CMOS voltage-mode quaternary logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
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A multi-valued Logic (MVL) pass gate is an important element to configure multi-valued logic. Multiple logical levels which are different from binary pass gates are required to be discriminated in MVL pass gates [1]. In this paper, we designed the Quaternary MIN (QMIN)/negated MIN (QMIN) gate, the Quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gate. And also we designed Quaternary Truncated Difference (QTD) gate using vMOS down literal circuit (DLC). DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed by vMOS DLC. The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltages and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.