A cell library for low power high performance CMOS voltage-mode quaternary logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
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A new multiple-valued current-mode (MVCM) integratedcircuit based on dynamic source-coupled logic (SCL) isproposed for low-power VLSI applications. The use of aprecharge-evaluate logic style makes steady current flow cutoff, thereby greatly saving the power dissipation. A combinationof SCL and dynamic logic styles makes it possibleto reduce the power dissipation while maintaining a high-speedswitching capability due to small input-voltage swingwith SCL. As a typical example of a high-performancearithmetic circuit, a radix-2 signed-digit adder based on theproposed dynamic SCL is implemented in a 0.18-µm CMOStechnology. Its power dissipation is reduced to about 33percent in comparison with that of the corresponding binaryCMOS implementation under the normalized switching delay.