A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
SystemC-based Design Methodology for Reconfigurable System-on-Chip
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
A dynamically reconfigurable packet-switched network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Performance of partial reconfiguration in FPGA systems: A survey and a cost model
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems
Towards rapid dynamic partial reconfiguration in video-based driver assistance systems
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Design space exploration for partially reconfigurable architectures in real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Real-Time Image Processing
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Signal and image processing applications require a lot of computing resources. For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order to reach the performances required by the product roadmaps. Nevertheless, FPGA designs are static, which raises a flexibility issue with new complex or software defined applications like software-defined radio (SDR). In this scope, dynamic partial reconfiguration (DPR) is used to bring a virtualization layer upon the static hardware of FPGA. During the last decade, DPR has been widely studied in academia. Nevertheless, there are very few real applications using it, and therefore, there is a lack of feedback providing relevant issues to address in order to improve its applicability. This paper evaluates the interest and limitations when using DPR in professional electronics applications and provides guidelines to improve its applicability. It makes a fair evaluation based on experiments made on a set of signal and image processing applications. It identifies the missing elements of the design flow to use DPR in professional electronics applications. Finally, it introduces a fast reconfiguration manager providing an 84-time improvement compared to the vendor solution.