Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Performance Evaluation of an Adaptive FPGA for Network Applications
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the conference on Design, automation and test in Europe
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
PDPR: fine-grained placement for dynamic partially reconfigurable FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
An automatic tool flow for the combined implementation of multi-mode circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
| Hi-index | 0.00 |
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR). This model is introduced to calculate the expected reconfiguration time and throughput. In order to develop a realistic model we take into account all the physical components that participate in the reconfiguration process. We analyze the parameters that affect the generality of the model and the adjustments needed per system for error-free evaluation. We verify it with real measurements, and then we employ it to evaluate existing systems presented in previous publications. The percentage error of the cost model when comparing its results with the actual values of those publications varies from 36% to 63%, whereas existing works report differences up to two orders of magnitude. Present work enables a user to evaluate PR and decide whether it is suitable for a certain application prior entering the complex PR design flow.