PDPR: fine-grained placement for dynamic partially reconfigurable FPGAs

Authors:
Ruining He;Guoqiang Liang;Yuchun Ma;Yu Wang;Jinian Bian
Affiliations:
Dept. of Computer Science and Technology, Tsinghua University, Beijing, China;Dept. of Computer Science and Technology, Tsinghua University, Beijing, China;Dept. of Computer Science and Technology, Tsinghua University, Beijing, China;Electronic Engineering Department, Tsinghua University, Beijing, China;Dept. of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Year:
2012

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Abstract

Dynamic Partial Reconfiguration (DPR) optimizes conventional FPGA application by providing additional benefits. However, considering the arbitrariness during manual floorplan and the limitation of local search when placement, it must be effective and promising if we combine the two stages to build a global optimization structure. In this paper, a novel thought for DPR FPGAs (PDPR) is proposed which tries to offer a one-stop floorplan and placement service. Experimental results show our approach can improve 32.8% on total wire length, 48.5% on reconfiguration cost, and 36.9% on congestion.