Secure IP downloading for SRAM FPGAs
Microprocessors & Microsystems
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
Enabling certification for dynamic partial reconfiguration using a minimal flow
Proceedings of the conference on Design, automation and test in Europe
Designing secure systems on reconfigurable hardware
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Protocol for Secure Remote Updates of FPGA Configurations
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Multi-level reconfigurable architectures in the switch model
Journal of Systems Architecture: the EUROMICRO Journal
Security Primitives for Reconfigurable Hardware-Based Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
Proceedings of the Conference on Design, Automation and Test in Europe
Performance of partial reconfiguration in FPGA systems: A survey and a cost model
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Field programmable gate arrays (FPGAs) provide an attractive solution to developers needing custom logic for short time-to-market products. Products embedding FPGA system-on-chip solutions have the advantage in that they can be updated once deployed. New FPGA firmware may be loaded via manufacturer-supplied memory devices or remotely via a network connection. Recent FPGAs allow for self-reconfiguration, where the user-FPGA fabric caninternally modify its own configuration data. Using selfreconfiguration, configuration control protocols can be implemented in user logic. This allows new FPGA programming methods to be designed. We propose a versatile partial self-reconfiguration framework for FPGA field updates that customizes to specific applications, reduces reconfiguration times, and minimizes the need for external hardware. The framework provides flexibility in media sources and design security. A prototype using this framework is demonstrated on a Xilinx Virtex-II FPGA.