Designing secure systems on reconfigurable hardware

Authors:
Ted Huffmire;Brett Brotherton;Nick Callegari;Jonathan Valamehr;Jeff White;Ryan Kastner;Tim Sherwood
Affiliations:
Naval Postgraduate School, Monterey, CA;Special Technologies Laboratory, Santa Barbara, CA;University of California, Santa Barbara, CA;University of California, Santa Barbara, CA;University of California, Santa Barbara, CA;University of California, San Diego, La Jolla, CA;University of California, Santa Barbara, CA
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2008

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Abstract

The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers often have no choice but to use soft IP cores obtained from third parties, the cores operate at different trust levels, resulting in mixed-trust designs. The goal of this project is to evaluate recently proposed security primitives for reconfigurable hardware by building a real embedded system with several cores on a single FPGA and implementing these primitives on the system. Overcoming the practical problems of integrating multiple cores together with security mechanisms will help us to develop realistic security-policy specifications that drive enforcement mechanisms on embedded systems.