Face Recognition: Features Versus Templates
IEEE Transactions on Pattern Analysis and Machine Intelligence
System level design of real time face recognition architecture based on composite PCA
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An improved face recognition technique based on modular PCA approach
Pattern Recognition Letters
Journal of Cognitive Neuroscience
A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images
IEEE Transactions on Circuits and Systems for Video Technology
Designing secure systems on reconfigurable hardware
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Online EHW Pattern Recognition System Applied to Face Image Recognition
Proceedings of the 2007 EvoWorkshops 2007 on EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog: Applications of Evolutionary Computing
Exploration of heterogeneous FPGAs for mapping linear projection designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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We describe a flexible and efficient multilane architecture for real-time face recognition system based on modular Principal Component Analysis (PCA) method in a Field Programmable Gate Array (FPGA) environment. We have shown in [1] that modular PCA improves the accuracy of face recognition when the face images have varying expression and illumination. The flexible and parallel architecture design consists of multiple processing elements to operate on predefined regions of a face image. Each processing element is also parallelized with multiple pipelined paths/lanes to simultaneously compute weight vectors of the non-overlapping region, hence called multilane architecture. The architecture is able to recognize a face image from a database of 1000 face images in 11ms.