The design of the UNIX operating system
The design of the UNIX operating system
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Open implementation design guidelines
ICSE '97 Proceedings of the 19th international conference on Software engineering
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Impulse: Building a Smarter Memory Controller
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Architectural adaptation for application-specific locality optimizations
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Designing secure systems on reconfigurable hardware
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Security Primitives for Reconfigurable Hardware-Based Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Formal Modeling and Verification of Security Property in Handel C Program
International Journal of Secure Software Engineering
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Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase performance. In the Morph/AMRM system, we are exploring the addition of reconfigurable logic, deeply integrated with the processor core, employing the reconfigurability to manage the cache, datapath, and pipeline resources more effectively. However, integration of reconfigurable logic introduces significant protection and safety challenges for multiprocess execution. We analyze the protection structures in a state of the art microprocessor core (R10000), identifying the few critical logic blocks and demonstration that the majority of the logic in the processor core can be safely reconfigured. Subsequently, we propose a protection architecture for the Morph/AMRM reconfigurable processor which enables nearly the full range of power of reconfigurability in the processor core while requiring only a small number of fixed logic features to ensure safe, protected multiprocess execution.