Hardware Description Languages: Concepts and Principles
Hardware Description Languages: Concepts and Principles
Model checking software architecture specifications in SAM
SEKE '02 Proceedings of the 14th international conference on Software engineering and knowledge engineering
Maude: specification and programming in rewriting logic
Theoretical Computer Science - Rewriting logic and its applications
Membership algebra as a logical framework for equational specification
WADT '97 Selected papers from the 12th International Workshop on Recent Trends in Algebraic Development Techniques
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Rewriting-Based Techniques for Runtime Verification
Automated Software Engineering
Reconfigurable Security Support for Embedded Systems
HICSS '06 Proceedings of the 39th Annual Hawaii International Conference on System Sciences
An approach to web services oriented modeling and validation
Proceedings of the 2006 international workshop on Service-oriented software engineering
Modeling, validating and automating composition of web services
ICWE '06 Proceedings of the 6th international conference on Web engineering
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Introduction to Embedded System Design Using Field Programmable Gate Arrays
Introduction to Embedded System Design Using Field Programmable Gate Arrays
Policy-driven memory protection for reconfigurable hardware
ESORICS'06 Proceedings of the 11th European conference on Research in Computer Security
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Multi-million gate system-on-chip SoC designs easily fit into today's Field Programmable Gate Arrays FPGAs. As FPGAs become more common in safety-critical and mission-critical systems, researchers and designers require information flow guarantees for the FPGAs. Tools for designing a secure system of chips SOCs using FPGAs and new techniques to manage and analyze the security properties precisely are desirable. In this work we propose a formal approach to model, analyze and verify a typical set of security properties-noninterference-of Handel C programs using Petri Nets and model checking. This paper presents a method to model Handel C programs using Predicate Transition Nets, a type of Petri Net, and define security properties on the model, plus a verification approach where security properties are checked. Three steps are used. First, a formal specification on the Handel C description using Petri Nets is extracted. Second, the dynamic noninterference properties with respect to the Handel C program statements are defined on the model. To assist in verification, a translation rule from the Petri Nets specification to the Maude programming language is also defined. Thus, the formal specification can be verified against the system properties using model checking. A case study of the pipeline multiplier is discussed to illustrate the concept and validate the approach.