DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Genetic Programming Using Self-Reconfigurable FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Efficient Metacomputation Using Self-Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
QUKU: A Two-Level Reconfigurable Architecture
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
On the Design of Two-Level Reconfigurable Architectures
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
A new decompression system for the configuration process of SRAM-based FPGAS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, we propose a concept for multi-level reconfigurable architectures with more than two levels of reconfiguration, and study these architectures theoretically and experimentally. The proposed architectures are extensions of 2-level reconfigurable architectures where the reconfiguration operations on the lowest level correspond to the reconfiguration operations of standard 1-level reconfigurable architectures, and the reconfigurable units are simple switches. It is shown that finding an optimal number of reconfiguration levels and a corresponding reconfiguration scheme that minimizes the number of reconfiguration bits for a given algorithm can be done in polynomial time. But finding the optimal number of reconfiguration levels is NP-hard for heterogeneous multi-level architectures, where the number of reconfiguration levels varies for the different reconfigurable units. Experimental results for different test applications show that 3-4 reconfiguration levels are optimal with respect to the number of reconfiguration bits needed. The number of reconfiguration bits is reduced by 35-86% compared to 1-level reconfiguration and by 8-34% compared to 2-level reconfiguration. The heterogeneous architecture reduces the number of necessary reconfiguration bits by additional 1-5% and also needs less SRAM cells.