EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Design and performance evaluation of virtual-channel based NoC
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Reconfigurable Networks on Chip: DRNoC architecture
Journal of Systems Architecture: the EUROMICRO Journal
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
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This paper presents the design of an adaptable NoC for FPGA based dynamically reconfigurable SoCs. At runtime, switches can be added or removed from the network, allowing to adapt the NoC to the number, size and location of currently configured hardware modules. By using dynamic routing tables, reconfiguration can be done without stopping or stalling the NoC. The proposed architecture avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs.