Learning-based adaptation to applications and environments in a reconfigurable network-on-chip

Authors:
Jih-Sheng Shen;Chun-Hsian Huang;Pao-Ann Hsiung
Affiliations:
National Chung Cheng University, Chiayi, Taiwan, ROC;National Chung Cheng University, Chiayi, Taiwan, ROC;National Chung Cheng University, Chiayi, Taiwan, ROC
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

Citing 5
Cited 2

Operating-system controlled network on chip

Proceedings of the 41st annual Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A dynamically reconfigurable packet-switched network-on-chip

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption

Computers and Electrical Engineering
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both have varying run-time requirements on reliability and power-efficiency. To meet these requirements, we propose a novel Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture which allows processing elements, routers, and data encoding methods to be reconfigured at runtime. Further, an intelligent selection of encoding methods is achieved through a REasoning And Learning (REAL) framework at run-time. An instance of PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to a conventional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of a conventional NoC by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. Experiments have thus shown that PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption, at the same amount of overheads in performance and hardware usage.