ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
Measuring the quality of an artificial hormone system based task mapping
Autonomics '08 Proceedings of the 2nd International Conference on Autonomic Computing and Communication Systems
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Moths: mobile threads for on-chip networks
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Dynamic decentralized mapping of tree-structured applications on NoC architectures
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Power-aware run-time incremental mapping for 3-D networks-on-chip
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Moths: Mobile threads for on-chip networks
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A self-adaptive heterogeneous multi-core architecture for embedded real-time video object tracking
Journal of Real-Time Image Processing
Pipelets: self-organizing software pipelines for many-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Smart hill climbing for agile dynamic mapping in many-core systems
Proceedings of the 50th Annual Design Automation Conference
A divide and conquer based distributed run-time mapping methodology for many-core platforms
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IPs in a scalable way. Applications running in MPSoCs execute a varying number of tasks simultaneously, and their number may exceed the available resources, requiring task mapping to be executed at runtime to meet real-time constraints. Most works in the literature present static MPSoC mapping solutions. Static mapping defines a fixed placement and scheduling, not appropriate for dynamic workloads. Task migration has also been proposed for use in MPSoCs, with the goal to relocate tasks when performance bottlenecks are identified. This work investigates the performance of mapping heuristics in NoC-based MPSoCs with dynamic workloads, targeting NoC congestion minimization, a key cost function to optimize the NoC performance. Here, tasks are mapped on the fly, according to communication requests and the load in the NoC links. Results show execution time and congestion reduction when congestion-aware mapping heuristics are employed.