ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A dynamically reconfigurable packet-switched network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
HW-SW emulation framework for temperature-aware design in MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
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New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for the high performance Embedding System. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its extensibility and power efficiency. The router is the fundamental unit of NoC. In this paper, a NoC prototype which consists of 6 ARM compatible cores and a router-based on-chip network is designed, and implements on a FPGA device. Different from the prototypes which we formerly designed, this prototype comprises more cores, and virtual-channel routers instead of basic routers. Specially, to evaluate the network performance, we present a run-time network monitor system, which can monitor the performance of on-chip network by calculating the performance parameters, such as average latency and throughput. The experimental results show that this prototype with 2×3 virtual-channel routers has less average latency than the former basic router prototype, and improves the throughput by up to 62%. Furthermore, JPEG decoding application is applied on this prototype, which steadily works at 50MHZ. And the decoding speed of system is very fast because of 2 decoding lane.