Multiple Si layer ICs: motivation, performance analysis, and design implications
Proceedings of the 37th Annual Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Leveraging 3D Technology for Improved Reliability
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Static and dynamic temperature-aware scheduling for multiprocessor SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient microarchitecture policies for accurately adapting to power constraints
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Distributed peak power management for many-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads
IPDPS '11 Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium
MLP-Aware instruction queue resizing: the key to power-efficient performance
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Nowadays, chip multiprocessors (CMPs) are the new standard design for a wide range of microprocessors: mobile devices (in the near future almost every smartphone will be governed by a CMP), desktop computers, laptop, servers, GPUs, APUs, etc. This new way of increasing performance by exploiting parallelism has two major drawbacks: off-chip bandwidth and communication latency between cores. 3D die-stacked processors are a recent design trend aimed at overcoming these drawbacks by stacking multiple device layers. However, the increase in packing density also leads to an increase in power density, which translates into thermal problems. Different proposals can be found in the literature to face these thermal problems such as dynamic thermal management (DTM), dynamic voltage and frequency scaling (DVFS), thread migration, etc. In this paper we propose the use of microarchitectural power budget techniques to reduce peak temperature. In particular, we first introduce Token3D, a new power balancing policy that takes into account temperature and layout information to balance the available per core power along other power optimizations for 3D designs. And second, we analyze a wide range of floorplans looking for the optimal temperature configuration. Experimental results show a reduction of the peak temperature of 2-26°C depending on the selected floorplan.