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Aggressive technology scaling over the years has helped improve processor performance but has caused a reduc- tion in processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards transient faults. An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors. A potential solution to mitigate the impact of such errors is redundancy via an in-order checker processor. Emerging 3D chip technology promises increased pro- cessor performance as well as reduced power consump- tion because of shorter on-chip wires. In this paper, we leverage the "snap-on" functionality provided by 3D inte- gration and propose implementing the redundant checker processor on a second die. This allows manufacturers to easily create a family of "reliable processors" without sig- nificantly impacting the cost or performance for customers that care less about reliability. We comprehensively eval- uate design choices for this second die, including the ef- fects of L2 cache organization, deep pipelining, and fre- quency. An interesting feature made possible by 3D inte- gration is the incorporation of heterogeneous process tech- nologies within a single chip. We evaluate the possibility of providing redundancy with an older process technology, an unexplored and especially compelling application of die heterogeneity. We show that with the most pessimistic as- sumptions, the overhead of the second die can be as high as either a 7 °C temperature increase or a 8% performance loss. However, with the use of an older process, this over- head can be reduced to a 3 °C temperature increase or a 4% performance loss, while also providing higher error re- silience. Keywords: reliability, redundant multi-threading, 3D die-stacking, parameter variation, soft errors, dynamic timing errors, power-efficient microarchitecture, on-chip temperature.