A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

Authors:
Zhen Zhang;Alain Greiner;Sami Taktak
Affiliations:
Univ Pierre et Marie Curie & LIP6-SOC, Paris, France;Univ Pierre et Marie Curie & LIP6-SOC, Paris, France;Univ Pierre et Marie Curie & LIP6-SOC, Paris, France
Venue:
Proceedings of the 45th annual Design Automation Conference
Year:
2008

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Abstract

In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to fault-tolerant, Massively Parallel Multi-Processors Systems on Chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router).