An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes
IEEE Transactions on Computers
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
Fault-Tolerant Wormhole Routing in Meshes without Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
IEEE Transactions on Computers
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Microarchitectures for Managing Chip Revenues under Process Variations
IEEE Computer Architecture Letters
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Rigel: an architecture and scalable programming interface for a 1000-core accelerator
Proceedings of the 36th annual international symposium on Computer architecture
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Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures, leading to a loss in core yield. Cores in a many-core architecture become non-operational because of the direct effect of process variations or indirectly because of the core-interconnect fabric failing to provide total resilience to faults on the fabric itself. Therefore, two ways to increase core yield are (a) reduce the clock frequency (so more cores can be clocked), and (b) devise a more robust, fault-tolerant interconnect fabric (so fewer cores become isolated). This work advocates for reducing the clock frequency as a more cost-effective solution to increase the core yield and the overall throughput performance of mesh-based many-core architectures.